Price Per Quantity
| JEDEC Std 30 Outline Code: | S-CPGA-P |
| Gate Capacity: | 6400 |
| Digital Input V Max (V): | 7.5 |
| Configurable Logic Blocks: | 224 |
| VIL Max. (CMOS) (V): | 1.0 |
| Vsup (+) Maximum (V): | 7.0 |
| Maximum Toggle Rate: | 70M |
| VOH Min.: | 3.86 |
| Logic Level Family: | CMOS and T |
| @IOH (test): | 4.0m |
| VIL Max. (TTL) (V): | 0.8 |
| Program Data (Bits): | 46064 |
| @Iol (A): | 4.0m |
| VOL Max.: | 0.4 |
| Number of User I/Os: | 110 |
| Quiescent Current Max (CMOS): | 500u |
| Nom. Pos. Supp: | 5 |
| VIH Min. (TTL) (V): | 2.0 |
| Quiescent Current Max (TTL): | 10m |
| VIH Min. (CMOS) (V): | 3.5 |
| Package Body Material: | Ceramic |
